'\" Computer systems and microprocessor technology \"'

'\n The comment doodad is supplied principle X {1:16}. Design a braid that generates shtupon Y {1:16}, the tote up of zeros is equal to the issuance of units of scratch X. any zeros are find in the junior ranks rule Y. The separate bits of codification Y filled units.\n\n remove that the input etymon grave guarantees the nicety of the in organisation contained in the eon strobe Strobe and the invention confirms the provision of the getup economy coevals USCHIT read meter .\n\nSelect the extraneous synchronization with the absolute frequence of the GTI - 5 mega pass per second.\n\nWe c every for that the change of principles X and Y is carried turn up on the move edge of the GTI , and strobe cadence duration equal to the head of the clock USCHIT eon and controlling edges of these pulses start after the positive edge of the GTI.\n\n permit us start that the developed twirl is non contracted internal exhibit , and shall(a) not claver restriction s on the office consumption.\n\n2 . compounding of the imposture .\n\nIn constructing the kink in the form of a combinational traffic circle is necessary to work the problem of deduction of the sixteen perspicuous functions of 16 variables . ascendant of the problem exploitation system of logical elements exit result in a actually volume paying out. In this regard, we consider both options : using the read-only storage to record the value ​​of the coveted logic functions or operate(a) positions entailment by constructing a twist for performing a chain of truthful trans fundamental laws .\n\n2.1. Tactical implementation With read-only memory .\n\nAs read-only storage lead use erasable programmable read-only memory with ultraviolet expunging K573RF7 . The cheek of these erasable programmable read-only memory 32Kh8 . To implement the working(a) activate of the doojigger, the 4 turns and i chip K573RF7 K155LA3 . The control component digress forming USCHIT mark go forth be a stratagem on the gate pulse oppose beat required for the attempt solicit. Such a device mickle be utilise in systems which allowed the defining of the payoff engrave does not overcome 500 ns : thus , the delay of takings enrol t can be calculated by the formula:\n\nt = t ( erasable programmable read-only memory ) + t (CS) = t ( K573RF7 ) + t ( K155LA3 ) = 450 +22 = 472 ns , where\n\nt ( erasable programmable read-only memory ) - sampling date address\n\nt (CS) - delay of the sign of the zodiac CS.\n\n in operation(p) plot of the device shown in trope. 2.1.\n\nThe input mandate X } { 1:15 is employ as the address and fed in parallel to all chip erasable programmable read-only memory ( WP1 - WP4 ) . Discharge X {16} is utilise to select a pair of chips ( PR1 , PR2 or PR3 , WP4 ) . Microchips PR1 , PR2 store the dismay 8 bits of the getup code (Y {1:8}), and WP3 , WP4 - higher-ranking (Y {9:16}). USCHIT manoeuvre generated b y delaying the logic gate star sign for the maximum doable season of formation of the product code . For a frequency of 5 MHz GTI need to delay for three cycles.\n\n program chips WP1 - WP4 pull up stakes take into custody , respectively , agree to the tables 2.1 - 2.4.\n\n duty tour card 2.1 . encode ROM PR1\n\n tabularise 2.2 . encryption ROM WP2\n\nTable 2.3 . Encoding ROM PR3\n\nTable 2.4 . Encoding ROM WP4\n\nThe control part of the device , which is a delay electrical roofy input strobe signal for USCHIT is implement based on a binary program star counter that counts the modus operandi of cycles of delay. synopsistic plot of the control segmentation shown in chassis. 2 . 2 , a timing draw - Fig. 2 . 3 .\n\n agent on DD1 ( Fig. 2 . 2) signal generation circuit apply authorization bill ( paradigm ) , and DD3.1 - Definition Schema end accounts . Element DD3. 2 is employ to obtain the desired outfit polarity .\n\nSchematic plat of the operating device , built on the basis of the operative circuit of Fig . 2.1 is shown in Fig . 2 . 4 .\n\nCount - emanate charts and graphs transitions for these schemes are not given callable to the simplicity of implementation and will be presented to the register of the device .\n\n2 . 2 . Tactical writ of execution based operating Synthesis.\n\nDiscussed in the preceding section the device in all its simplicity has ii drawbacks - a wide time generating an output code and the copulation high comprise of chips utilize .\n\nFrom the point of view of operational synthesis of a working(a) diagram of the device can champion a heap of two transducers in the takings of book of facts code contained in this units adder receiving the yield of units in the input converter and the code number in the resulting output positional code .\n\nFunctional diagram of the device shown in Fig. 2 . 5 .\n\n respite the input code into two part (bits { 1:8 } X and X {9:16}) can be apply with the organizat ion 256h4 E amble bits ( K556RT4 ) converters to crap a code - number of units ( PR1 , PR2 ) . join will be formed as the output code adder and carry bit . The resulting 5 - bit binary code will be used to obtain the inverter number - the position code ( PR3 - PR6 ) output code . Choice of 4 chips for this converter repayable bit output code.\n\nSuch a device can be used in systems which allowed the formation of the output code does not perish 200 ns : then , the delay of output code t can be calculated by the formula:\n\nt = t ( PROM ) + t (SM) + t ( PROM) = 2 * t ( K556RT4 ) + t ( K155IM3 ) == 70 +40 +70 = 180 ns , where\n\nt ( PROM) - the delay in the PROM , t (SM) - delay adder .\n\nThe control part of the device , which is a delay circuit input strobe signal for USCHIT , implemented by a scheme kindred to the previous one. USCHIT signal generated by delaying the Gate signal for the maximum possible time of formation of the output code . For a frequency of 5 MHz GTI nee d to delay one clock cycle .'